UVM Phasing Interview Questions

Questions on UVM execution phases, ranging from basic order to advanced phase jumping and domains.

Beginner Level

Fundamentals
List the standard UVM phases in their execution order.
  1. build_phase (Function, Top-down)
  2. connect_phase (Function, Bottom-up)
  3. end_of_elaboration_phase (Function, Bottom-up)
  4. start_of_simulation_phase (Function, Bottom-up)
  5. run_phase (Task, Parallel, Time-consuming)
  6. extract_phase (Function, Bottom-up)
  7. check_phase (Function, Bottom-up)
  8. report_phase (Function, Bottom-up)
  9. final_phase (Function, Top-down)
Which phases are Top-Down and which are Bottom-Up? Why?

Top-Down: `build_phase` and `final_phase`. Build must be top-down so parents are created before they try to create children.

Bottom-Up: `connect_phase` and most others. Connect is bottom-up so you connect children ports before connecting the parent to the outside.

Intermediate Level

Industry Standard
What is the difference between `run_phase` and the runtime phases (reset, configure, main...)?

UVM 1.2 introduced 12 runtime sub-phases (pre_reset, reset, ... main, ... shutdown). These run sequentially. The `run_phase` runs in parallel to these 12 phases.

Advice: Avoid mixing them. If you use `run_phase`, stick to it. If you use `main_phase`, stick to the sub-phases.

How do you prevent a test from ending immediately in `run_phase`?

You must raise an objection. UVM naturally ends when no component has a raised objection.

phase.raise_objection(this);
// Do work
phase.drop_objection(this);

Advanced Level

Expert
What is a Phase Jump? How is it implemented?

Phase jumping allows you to abort the current phase and move to another (backward or forward). Useful for Warm Resets.

phase.jump(uvm_phase::get_phase_by_name("reset_phase"));

Impact: All components are killed in the current phase and restarted in the target phase.

Can you add a custom phase to the UVM schedule? (Tricky)

Yes. You need to extend `uvm_phase`, create a singleton instance, and insert it into the schedule using `uvm_domain::add_phase()`. For example, inserting a `training_phase` for link training before the `main_phase`.

You will need to manually call `super.connect_phase()` or rely on the `uvm_phase` base methods to ensure it's integrated correctly.

How would you debug a simulation that never ends (Hang)?

1. Check Objections: Use `+UVM_OBJECTION_TRACE` to see who raised but never dropped an objection.

2. Check Timeout: Use `+UVM_TIMEOUT=1000000ns,YES` to force a stop and print stack traces.

3. Check Deadlock: Drivers waiting for items that never come (sequencer empty but objection raised).