Digital Design Interview Questions

Collection of fundamental digital design questions for VLSI interviews.

Digital Design Strategy for Verification Engineers

Even if you are applying for a functional verification role (UVM/SV), 30-40% of the interview will test your core digital design fundamentals.

1. Clock Domain Crossing (CDC)

The most common topic. Know the difference between Metadata CDC (Gray codes, Handshakes) and Data CDC (FIFOs).

2. Finite State Machines (FSM)

You will be asked to code a sequence detector (e.g., "1011"). Practice coding both Mealy (output depends on input) and Moore machines.

Common "Gotcha" Questions:

  • FIFO Depth Calculation: Memorize the formula: `Depth = N * (1 - (f_rd / f_wr))`. Be ready to derive it.
  • Setup vs Hold Time: Which one is frequency independent? (Hold time). Why?
  • Glitch Analysis: How do you fix a glitch in a combinational circuit? (K-maps to find hazards).