- Separate Address/Control and Data Phases: Control and data flow independently.
- Unaligned Data Transfers: Uses byte strobes to handle unaligned start addresses.
- Burst-based Transactions: Only the start address is issued; the data follows in a burst.
- Separate Read and Write Channels: Full duplex communication (simultaneous Read/Write).
- Out-of-Order Transaction Completion: Allows high efficiency with disparate Slave latencies.
AXI Protocol Overview
Last updated: January
2026
The Advanced eXtensible Interface (AXI) is the highest performance AMBA interface, designed for high-frequency, high-bandwidth interconnects in modern SoCs.
Key Features
Why This Matters in Real Projects
AXI is the backbone of modern SoCs (CPUs, GPUs, DDR).
Understanding its 5-channel architecture and out-of-order transaction model is
crucial for debugging system deadlocks and optimizing interconnect bandwidth.
Why AXI Verification Often Fails
Even with 100% coverage, AXI bugs often escape to silicon because:
- "Polite" VIPs: Commercial VIPs often behave too nicely (always ready, ordered responses), masking RTL bugs that only appear with "rude" slaves.
- The 4KB Boundary Trap: Bursts crossing a 4KB address boundary must split into two transactions. forgetting this locks up the NoC.
- Ordering Violations: ID-based reordering logic is complex. Bugs here often look like data corruption, not protocol errors.
Comparison: AHB vs AXI
| Topology | Shared Bus | Multi-channel / Crossbar |
| Channels | Shared R/W | 5 Independent Channels |
| Performance | Medium | High |
Recommended Learning Path
If you're new to AXI, we recommend following this order:
- Channels & Handshake - The physical signaling layer
- Bursts & Addressing - How data is transferred
- Ordering & IDs - High-performance features
- Atomic Access - Multi-master synchronization